DK-DEV-5SGXEA7N【PDF 106/527 页】KIT DEV STRATIX V FPGA 5SGXEA7

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4-36

Automatic Switchover

SV51005

2014.01.10

The following clock switchover modes are supported in Stratix V PLLs:

? Automatic switchover — The clock sense circuit monitors the current reference clock. If the current

reference clock stops toggling, the reference clock automatically switches to inclk0 or inclk1 clock.

? Manual clock switchover — Clock switchover is controlled using the clkswitch signal. When the clkswitch

signal goes from logic low to logic high, and stays high for at least three clock cycles, the reference clock

to the PLL is switched from inclk0 to inclk1 , or vice-versa.

? Automatic switchover with manual override — This mode combines automatic switchover and manual

clock switchover. When the clkswitch signal goes high, it overrides the automatic clock switchover

function. As long as the clkswitch signal is high, further switchover action is blocked.

Automatic Switchover

Stratix V PLLs support a fully configurable clock switchover capability.

Figure 4-35: Automatic Clock Switchover Circuit Block Diagram

This figure shows a block diagram of the automatic switchover circuit built into the PLL.

clkbad[0]

clkbad[1]

activeclock

Clock

Sense

clksw

Switchover

State Machine

inclk0

Clock Switch

Control Logic

clkswitch

inclk1

Multiplexer

Out

N Counter

refclk

PFD

fbclk

When the current reference clock is not present, the clock sense block automatically switches to the backup

clock for PLL reference. You can select a clock source as the backup clock by connecting it to the inclk1

port of the PLL in your design.

The clock switchover circuit sends out three status signals — clkbad[0] , clkbad[1] , and activeclock — from

the PLL to implement a custom switchover circuit in the logic array.

In automatic switchover mode, the clkbad[0] and clkbad[1] signals indicate the status of the two clock

inputs. When they are asserted, the clock sense block detects that the corresponding clock input has stopped

toggling. These two signals are not valid if the frequency difference between inclk0 and inclk1 is greater

than 20%.

The activeclock signal indicates which of the two clock inputs ( inclk0 or inclk1 ) is being selected as the

reference clock to the PLL. When the frequency difference between the two clock inputs is more than 20%,

the activeclock signal is the only valid status signal.

Note: Glitches in the input clock may cause the frequency difference between the input clocks to be more

than 20%.

Altera Corporation

Clock Networks and PLLs in Stratix V Devices

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